september 2010 ? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 fin1108 ? lvds 8-port, high-speed repeater fin1108 ? lvds 8-port, high-speed repeater features ? greater than 800mbps data rate ? 3.3v power supply operation ? 3.5ps maximum random jitter and 135ps maximum deterministic jitter ? wide rail-to-rail common mode range ? lvds receiver inputs accept lvpecl, hstl, and sstl-2 directly ? ultra-low power consumption ? 20ps typical channel-to-channel skew ? power-off protection ? 7.5kv hbm esd protection ? meets or exceeds the tia/eia-644-a lvds standard ? 48-lead tssop package ? open-circuit fail-safe protection ? v bb reference output descriptions this eight-port repeater is designed for high-speed interconnects utilizing low voltage differential signaling (lvds) technology. the fin1108 accepts and outputs lvds levels with a typical differential output swing of 330mv, which provides low emi at ultra-low power dissipation even at high frequencies. the fin1108 provides a v bb reference for ac coupling on the inputs. in addition, the fin1108 can directly accept lvpecl, hstl, and sstl-2 for translation to lvds. ordering information part number operating temperature range package packing method fin1108mtd -40 to +85c 48-lead, thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide tube fin1108mtdx -40 to +85c 48-lead, shrink small outline package (tssop), jedec mo-153, 6.1mm wide tape and reel
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 2 fin1108 ? lvds 8-port, high-speed repeater pin configuration figure 1. pin configuration pin definitions pin # name description 1,2,23,37,36 gnd ground. 3 /en 12 inverting driver enable for d out1 and d out2 . 4,7,8,11,14,17,18,21 r in1- ,r in2- ,r in3- ,r in5- r in6- ,r in7- ,r in8- inverting lvds input. 5,6,9,10,15,16,19,20 r in1+ ,r in2+ ,r in3+ ,r in5+ r in6+ ,r in7+ ,r in8+ non-inverting lvds input. 12,25,26,47,48 vcc power supply pin. 13 en driver enable for all outputs. 22 /en 34 inverting driver enable for d out3 and d out4 . 24 v bb reference voltage output. 27 /en 56 inverting driver enable for d out5 and d out6 . 28,31,32,35,38,41,42,45 d out8- ,d out7- ,d out6- ,d out5- d out4- ,d out3- ,d out2- ,d out1 - inverting drive output. 29,30,33,34,39,40,43,44 d out8+ ,d out7+ ,d out6+ ,d out5+ d out4+ , d out3+ ,d out2+ ,d out1 + non-inverting drive output. 46 /en 78 inverting driver enable for d out7 and d out8 .
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 3 fin1108 ? lvds 8-port, high-speed repeater functional diagram figure 2. functional diagram table 1. function table inputs outputs en /en xx d in+ d in- d out+ d out- high low high low high low high low low high low high high low fail-safe high low don?t care high don?t care don?t care high impedance high impedance low don?t care don?t care don?t care high impedance high impedance
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 4 fin1108 ? lvds 8-port, high-speed repeater absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 +4.6 v v in lvds dc input voltage -0.5 +4.6 v v out lvds dc output voltage -0.5 +4.6 v i osd driver short-circuit current continuous 10 ma t stg storage temperature range -65 +150 c t j junction temperature +150 c t l lead temperature, soldering, 10 seconds +260 c esd human body model, jesd22-a114 7500 v machine model, jedec: jesd22-a115 400 recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v ? v id ? magnitude of differential voltage 100 mv to v cc v v ic common mode voltage range (0v + ? v id ? /2 ) (v cc - ? v id ? /2 ) v t a operating temperature -40 +85 c
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 5 fin1108 ? lvds 8-port, high-speed repeater dc electrical characteristics typical values are at t a =25c with v cc =3.3v. symbol parameter conditions min. typ. max. units v th differential input threshold high v ic =+0.05v, + 1.2v, or v cc - 0.05v figure 3 100 mv v tl differential input threshold low v ic =+0.05v, + 1.2v, or v cc - 0.05v figure 3 -100 mv v ih input high voltage (en or /en) 2.0 v cc v v il input low voltage (en or /en) gnd 0.8 v v od output differential voltage r l =100 , driver enabled, figure 4 250 330 450 mv v od v od magnitude change from differential low-to-high 25 mv v os offset voltage 1.125 1.230 1.375 v v os offset magnitude change from differential low-to-high 25 mv i os short-circuit output current d out+ =0v and d out- =0v, driver enabled -3.4 -6.0 ma v od =0v, driver enabled 3.4 6.0 ma i in input current (en, /en, d inx+ , d inx- ) v in =0v to v cc , other input=v cc or 0v for differential input 20 a i off power-off input or output current v cc =0v, v in or v out =0v to 3.6v 20 a i ccz disabled power supply current drivers disabled 20 ma i cc power supply current drivers enabled, any valid input condition 80 ma i oz disabled output leakage current driver disabled, d out+ =0v, to 3.6v or d out- =0v to 3.6v 20 a v ic common mode voltage range v id /2 v cc - (v id /2) v c in input capacitance enable input 3 pf lvds input 3 c out output capacitance 3 pf v bb output reference voltage v cc =3.3v, i bb =0 to -275 a 1.125 1.200 1.375 v
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 6 fin1108 ? lvds 8-port, high-speed repeater ac electrical characteristics typical values are at t a =25c with v cc =3.3v. symbol parameter conditions min. typ. max. units t plhd differential output propagation delay low-to-high r l =100 , c l =5pf v id =200mv to 450mv, v ic = v id /2 to v cc ? (v id /2) duty cycle=50% figure 3 0.75 1.10 1.75 ns t phld differential output propagation delay high-to-low 0.75 1.10 1.75 ns t tlhd differential output rise time (20% to 80%) 0.29 0.40 0.58 ns t thld differential output fall time (80% to 20%) 0.29 0.40 0.58 ns t sk(p) pulse skew |t plh - t phl | 0.02 0.20 ns t sk(lh) channel-to-channel skew (1) 0.02 0.15 ns t sk(hl) 0.02 0.15 t sk(pp) part-to-part skew (2) 0.5 ns f max maximum frequency (3)(4) 400 >630 mhz t pzhd differential output enable time from z to high r l =100 , c l =5pf figure 4, figure 5 3.0 5.0 ns t pzld differential output enable time from z to low 3.1 5.0 ns t phzd differential output disable time from high to z 2.2 5.0 ns t plzd differential output disable time from low to z 2.5 5.0 ns t dj lvds data jitter, deterministic v id =300mv, prbs=2 23 -1, v ic =1.2v at 800mbps 80 135 ps t rj lvds clock jitter, random (rms) v id =300mv v ic =1.2v at 400mbps 1.9 3.5 ps notes : 1. t sk(lh) , t sk(hl) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. 2. t sk(pp) is the magnitude of the difference in propagation del ay times between any specified terminals of two devices switching in the same direction (either low-to-high or high-to-low) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. 3. passing criteria for maximum frequency is the output v od >250mv and the duty cycle is better than 45% / 55% with all channels switching. 4. output loading is transmission-line environment only; c l is <1pf of stray test fixture capacitance.
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 7 fin1108 ? lvds 8-port, high-speed repeater test diagrams figure 3. differential receiver voltage definitions figure 4. differential driver dc test circuit notes: all lvds input pulses have frequency=10mhz, t r or t f <0.5ns. c l includes all probe and jig capacitance. figure 5. differential driver propagation delay and transition time test circuit figure 6. ac waveform notes: all lvttl input pulses have frequency=10mhz, t r or t f <2ns. c l includes all probe and jig capacitance. figure 7. differential driver enable and disable circuit figure 8. enable and disable ac waveforms
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 8 fin1108 ? lvds 8-port, high-speed repeater physical dimensions figure 9. 48-lead, thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
? 2002 fairchild semiconductor corporation www.fairchildsemi.com fin1108 ? rev. 1.0.4 9 fin1108 ? lvds 8-port, high-speed repeater
|
